Microprocessors commonly use dynamic power management techniques to manage power usage. Normally, dynamic power management for microprocessors is accomplished through activity detection circuitry that is located in the microprocessor and coupled to a centralized, front side bus (FSB). The activity detection circuitry is adapted to detect conditions under which certain units should be turned on or off and to adjust the power levels of these units appropriately.
Traditionally, the activity detection circuitry has provided acceptable performance because such circuitry was physically separated from the power-controlled units by only a short distance. However, bus architectures are moving away from FSB architectures and are beginning to utilize point-to-point architectures. One type of point-to-point architecture is referred to as “Common System Interconnect” or “CSI”. This architecture will likely experience difficulties in power management.
One reason for experiencing such difficulties is that CSI-style distributed systems support implementations where the power management circuitry and the power-controlled units are placed on different integrated circuits, but are connected by CSI links. As a result, conventional activity detection circuitry cannot effectively hide the latency to turn on/off the units from the performance aspects of the system since it cannot provide adequate lead time to circuitry of these units to turn power on or off.